rtl-llm/qwen2.5coder-7b-origen-vhdl-verilog-len768
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8B
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rtl-llm/qwen2.5coder-7b-origen-all-ordered-verilog-first
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8B
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rtl-llm/qwen2.5coder-7b-origen-vhdl-verilog-vhdl-pymtl
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8B
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rtl-llm/qwen2.5coder-7b-origen-all-ordered-len768
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8B
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rtl-llm/qwen2.5coder-7b-origen-vhdl-verilog
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8B
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rtl-llm/qwen2.5coder-7b-origen-vhdl-4.1-4o-v2
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8B
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rtl-llm/qwen2.5coder-7b-origen-verilog-v2
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8B
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rtl-llm/qwen2.5coder-7b-verilog-completion-gpt-4o-augmented
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8B
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rtl-llm/qwen2.5coder-7b-origen-verilog
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8B
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rtl-llm/qwen2.5coder-7b-origen-all-shuffled
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8B
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rtl-llm/qwen2.5-32b-coder-instruct-gpt_vhdl_normal_vhdl_combined
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33B
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rtl-llm/qwen2.5-32b-coder-instruct-gpt_vhdl
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33B
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rtl-llm/qwen2.5-32b-coder-instruct-vhdl_lowered_LORA
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33B
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rtl-llm/qwen2.5-32b-coder-instruct-vhdl_no_template
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33B
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rtl-llm/qwen-32b-data-ordered-based-on-performance
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33B
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rtl-llm/qwen3-14b-vhdl_yes_template
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15B
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rtl-llm/qwen3-14b-vhdl_no_template
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rtl-llm/qwen3-14b-base-vhdl_updated_template_2
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15B
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rtl-llm/qwen3-14b-base-vhdl_updated_template
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15B
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rtl-llm/qwen-32b-everything-with-warmup
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33B
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rtl-llm/qwen3-14b-base-vhdl
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15B
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rtl-llm/qwen-32b-everything
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33B
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rtl-llm/qwen-32b-FirRTL
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33B
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rtl-llm/qwen-32b-PyMTL-lora128
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33B
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rtl-llm/qwen-32b-BetterV
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33B
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rtl-llm/qwen-32b-PyMTL
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33B
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rtl-llm/qwen-7b-vhdl-corresponding_to_c2v_translatables
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8B
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rtl-llm/qwen-7b-vhdl-baseline
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8B
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rtl-llm/qwen-7b-vhdl-obfuscated
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8B
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rtl-llm/qwen-7b-c2v-translatable_to_vhdl
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8B
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